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AR# 47517

Zynq-7000 AP SoC, SMC - NAND with ECC might not Deassert CS between Data Transactions


The NAND flash controller normally deasserts the chip select (CS) between data transfers and keeps the chip select asserted between a data transaction and a command operation. This protocol is compatible with most devices. In certain modes of operation, the controller might incorrectly believe that it is about to perform a command operation after a data operation, and the controller keeps the chip select asserted between two data transactions.

This is avoided when ECC is disabled. When ECC is enabled:

  • Use full commands for writes
  • Read the ECC codes between the reading of blocks



Minor, refer to the Work-arounds.


  • Use the ECC block in full command mode for writes. Read ECC codes between blocks for reads.

  • If you are reading or writing more than one 512 byte block, ensure that the data crosses the 512 byte boundary in a single un-interrupted transaction.

Configurations Affected:

Systems that use NAND with ECC.

Device Revision(s) Affected:

All, no plan to fix. Refer to (Xilinx Answer 47916) Zynq-7000 AP SoC Silicon Revision Differences.

The SMC is designed to support NAND devices that require CS to be held low between data-phase accesses, as well as devices that do not have this requirement. To satisfy both types of memory, the ECC block will not de-assert CS after a block transfer has been completed if it is about to issue a command. However, in certain modes of operation (specifically when column-change commands are enabled and software is not reading ECC codes between blocks), SMC incorrectly assumes that it is about to perform an operation and cancels the request to de-assert the CS.

Impact Detail: Under the above mentioned conditions, CS will not be de-asserted. This could result in deadlock if data or code required to create the next transaction is stored through the same EBI.

AR# 47517
Date Created 05/23/2012
Last Updated 03/27/2013
Status Active
Type Design Advisory
  • Zynq-7000