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AR# 47518

Zynq-7000 AP SoC, SMC - Potential SRAM/NOR Data Error

Description

A potential SRAM/NOR data error can occur if all the write data of a transaction is contained in a single AXI data transfer cycle. Always perform writes that require multiple AXI data transfer cycles in the transaction.

Solution

Impact: Minor, refer to the Work-around Details.
Work-around: See Work-around Details.
Configurations Affected: Systems that use the SRAM/NOR interface. The NAND interface mode is unaffected.
Device Revision(s) Affected: All. No plan to fix. Refer to (Xilinx Answer 47916) - Zynq-7000 AP SoC Silicon Revision Differences.

Work-around Details:

  • Use a memory burst length that is long enough to contain more than one AXI beat (normally memory burst length of 4 will do this). This work-around has least impact on performance because AXI bursts of data (greater than 1 beat) are treated optimally on the memory interface. This work-around can be used provided the memory device supports back to back transactions without chip select being deasserted.
  • If the memory device requires chip select to be deasserted between bursts, then the best work-around is to set the refresh_period register to 1. This ensures the controller returns to idle between every transaction. This adds tTR idle cycles between each transaction of a burst that would otherwise have completed back to back.

 

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47916 Zynq-7000 AP SoC Devices - Silicon Revision Differences N/A N/A
AR# 47518
Date Created 05/23/2012
Last Updated 04/15/2013
Status Active
Type Design Advisory
Devices
  • Zynq-7000
  • Zynq-7000Q
  • XA Zynq-7000