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AR# 47518 Zynq-7000, SMC - Potential SRAM/NOR Data Error

Description

A potential SRAM/NOR data error can occur if all the write data of a transaction is contained in a single AXI data transfer cycle. Always perform writes that require multiple AXI data transfer cycles in the transaction.

Solution

Impact:

Minor, refer to the Work-around Details.

Work-around:

See Work-around Details below.

Configurations Affected:

Systems that use the SRAM/NOR interface. The NAND interface mode is unaffected.

Device Revision(s) Affected:

All, no plan to fix. Refer to (Xilinx Answer 47916) - Zynq-7000 Design Advisory Master Answer Record

Work-around Details:

  • Use a memory burst length that is long enough to contain more than one AXI beat (normally memory burst length of 4 will do this). This work-around has least impact on performance because AXI bursts of data (greater than 1 beat) are treated optimally on the memory interface. This work-around can be used provided the memory device supports back to back transactions without chip select being deasserted.
  • If the memory device requires chip select to be deasserted between bursts, then the best work-around is to set the refresh_period register to 1. This ensures the controller returns to idle between every transaction. This adds tTR idle cycles between each transaction of a burst that would otherwise have completed back to back.

Actions

AR# 47518
Date Created 05/23/2012
Last Updated 08/07/2012
Status Active
Type Design Advisory
Devices
  • Zynq-7000
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