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AR# 47519

Zynq-7000 AP SoC, SMC - NAND with ECC Misses Single Bit and some Double Bit Errors

Description

There is a defect in the coding of the ECC algorithm and it misses single-bit errors to bit 0 of byte 0 and fails to detect some double-bit error cases. Only the odd half of the parity calculation is being tested to check for pass/fail. When reading the data from NAND with the ECC enabled, in some specific cases, the results indicated in the registers are incorrect.

Solution

Impact: Major. There are three implications, see the Impact Details paragraphs. The work-arounds greatly reduce the likelihood of missing errors.
Work-arounds: Please see the Work-around Details.
Configurations Affected: Systems that use ECC with NAND.
Device Revision(s) Affected:
Refer to (Xilinx Answer 47916) - Zynq-7000 AP SoC Silicon Revision Differences.


Impact Details

There are three implications:

  1. A single-bit error in data bit 0 of byte 0 will not be detected. This error case will result in a false positive that the data has passed the error check.
  2. A single-bit error in the second 12 bits of the 3 parity bytes read from the spare area will incorrectly be identified as having passed the error check. The algorithm should flag the errors occurring in the spare area as uncorrectable failures.
  3. Some double-bit error cases are not correctly identified as uncorrectable failures.

    Double-bit Error Detection (Implication 3):
    • 90 double-bit errors out of a total possible 8485140 combinations (0.001%) are not correctly identified as uncorrectable failures. These 90 cases will result in a false positive that the data has passed the error check.
    • Both error bits in data-only bytes: All possible locations (8386560 total) will be correctly identified as uncorrectable failures.
    • Both error bits in parity-only bytes: 66 of the 276 possible errors are not identified as uncorrectable failures.
    • One bit in parity byte and one in data byte: 24 of the 98304 possible errors will not be identified as uncorrectable failures.

Work-around Details

There is a software work-around to the implication (1). If a single-bit error occurs to bit 0 of byte 0, the ECC register values return.

A more complex software work-around is to manually read the ECC parity data stored in the spare area, and then use software to calculate the ECC result independently of the hardware mechanism.

ecc_fail = 0 and ecc_correct = 1. This result uniquely identifies a single bit error to bit 0 of byte 0. The register values can be read to identify this case, and the bit error can be corrected with software.

 

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47916 Zynq-7000 AP SoC Devices - Silicon Revision Differences N/A N/A
AR# 47519
Date Created 05/23/2012
Last Updated 06/05/2013
Status Active
Type Design Advisory
Devices
  • Zynq-7000
  • XA Zynq-7000
  • Zynq-7000Q