We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 47521

Zynq-7000 AP SoC, DDR - DCI Quiet Mode Operation is not supported


The DDR I/O buffer (DDRIOB) DCI impedance adjustment mode (slcr.DDRIOB_DCI_CTRL [UPDATE_CONTROL]) should be set according to the Calibration table in Chapter 10 of the TRM v1.5 or later.


Impact: Trivial.
Work-around: None.
Configurations Affected: Systems that DDR in the PS.
Device Revision(s) Affected: Refer to (Xilinx Answer 47916) - Zynq-7000 AP SoC Silicon Revision Differences

January 2013: slcr.DDRIOB_DCI_CTRL.UPDATE_CONTROL must be set to '0' for DCI operation, to allow the VRN/VRP to sample the reference resistors.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47916 Zynq-7000 AP SoC Devices - Silicon Revision Differences N/A N/A
AR# 47521
Date Created 05/24/2012
Last Updated 02/19/2013
Status Active
Type Design Advisory
  • Zynq-7000