DDRIOB has issues with the DCI state machine and cannot dynamically determine the setting for proper impedance matching. This results in DDR2/DDR3 input termination and LPDDR2 output drive strength not matched to the DCI reference resistors.
Solution
Impact: Minor.
Work-around: None.
Configurations Affected: Systems using the DDR memory controller (DDR2, DDR3 and LPDDR2)
Device Revision(s) Affected: Refer to the Zynq-7000 AP SoC - Design Advisory Master Answer Record (Xilinx Answer 47916).