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AR# 47523

LogiCORE IP Video Scaler v5.0 and v7.00.a - Why do the AXI4-Lite register readbacks fail sometimes in simulation?

Description

Why do the AXI4-Lite register readbacks fail sometimes in simulation?

Solution

This is a known issue with Video Scaler v5.0 that is resolved in Video Scaler v6.00.a but resurfaced in Video Scaler v7.00.a. 

This occurs because the internal timeout on the AXI4-Lite interface is being asserted before the core can return the results of the register read request.

This issue is also addressed in the Video Scaler v5.0 Rev3 patch. 

To obtain the patch, see (Xilinx Answer 45439).

Also, you might see problems if the AXI4-Lite interface is multiple times faster than the Input Video clock.

If this is the case, it is recommended that you add some delay between consecutive reads and writes to the AXI4-Lite Interface.

A delay equal to the period of 1 clock on the Video In clock domain should be sufficient.

Note: The Video Scaler does not support behavioral simulation in EDK Projects.

For more information on how to simulate EDK Projects with Video IP, see (Xilinx Answer 34828).

For a detailed list of LogiCORE IP Video Scaler Release Notes and Known Issues, see (Xilinx Answer 31958).

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
45439 LogiCORE IP Video Scaler v5.0 - Patch Updates N/A N/A
31958 LogiCORE IP Video Scaler - Release Notes and Known Issues N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
45439 LogiCORE IP Video Scaler v5.0 - Patch Updates N/A N/A
31958 LogiCORE IP Video Scaler - Release Notes and Known Issues N/A N/A
AR# 47523
Date Created 05/08/2012
Last Updated 12/18/2014
Status Active
Type General Article
IP
  • Video Scaler