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AR# 47525

Zynq-7000 AP SoC, PS Clocks - Soft Reset of System Clocks does not Consistently Reset Clock Dividers to Default Values


Soft reset of system clocks does not consistently reset clock dividers to default values. Software must configure all clock dividers after a soft reset and not depend on default settings.



Minor, software should always reprogram the clocks subsystem.


After a soft reset, software should reprogram the clocks.

Configurations Affected:


Device Revision(s) Affected: Refer to (Xilinx Answer 47916) - Zynq-7000 Design Advisory Master Answer Record

Impact Details

The PS clock dividers might not get updated to their reset/default values.

If the PLL was shut off before the soft reset, immediately after the soft reset, the PS will use the clock from the PLL that has not finished turning on.

Work-around Details

After a soft reset, configure all clock dividers. This ensures that regardless of their state, the clock dividers are properly set following reset. Furthermore, the ARM PLL should not get shut off prior to the soft reset.

AR# 47525
Date Created 05/24/2012
Last Updated 11/12/2012
Status Active
Type Design Advisory
  • Zynq-7000