Impact: Minor, refer to the Work-around.
Work-around: To ensure that the PL is cleared during a reset cycle, pull-up or tie the PROGRAM_B_0 High and set the DEVCFG.CTRL[PCFG_PROG_B] register bit in the first stage boot loader before configuring the PL.
Configurations Affected: All.
Device Revision(s) Affected: Refer to
(Xilinx Answer 47916) - Zynq-7000 Design Advisory Master Answer Record
When the Boot ROM hands off execution to the first stage boot loader, the contents of the PL should have been cleared out. However, under certain circumstances, the PL might retain a full or partial configuration. Either one of the following circumstances can lead to this behavior:
- The PROGRAM_B_0 device pin is held Low after powering the device on and user configures the PL with a bitstream.
- The DEVCFG.CTRL[PCFG_PROG_B] bit is kept cleared (reset state) after powering the device on and user configures the PL with a bitstream.
- The PL does not retain its configuration during a reset cycle if at any time during device operation both DEVCFG.CTRL[PCFG_PROG_B] and the PROGRAM_B_0 device pin are High at the same time.