We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 47543

Zynq-7000 AP SoC, USB - ULPI Viewport Does Not Work With Extended Addresses


It is not possible to read or write the ULPI PHY extended register set (addresses 0x40 and greater) using the ULPI viewport. The write operation writes the address itself as data, and a read operation returns incorrect data.



Minor. A controller lock-up is not expected. The PHY registers that are affected and cannot be read through the ULPI Viewport are only the Reserved (0x40 to 0x7F) and Vendor-specific (0x80 to 0xFF) registers.


There is no work-around at this time.

Configurations Affected:

Systems that use the USB controller.

Device Revision(s) Affected: All, no plan to fix. Refer to (Xilinx Answer 47916) - Zynq-7000 Design Advisory Master Answer Record.
AR# 47543
Date Created 05/24/2012
Last Updated 08/23/2012
Status Active
Type Design Advisory
  • Zynq-7000