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AR# 47551

Zynq-7000, APU - ISB Instruction Is Counted In Performance Monitor Events 0x0C and 0x0D

Description

The ISB instruction is implemented as a branch in the Cortex-A9 microarchitecture. This implies that events 0x0C (software change of PC) and 0x0D (immediate branch) are asserted when an ISB occurs, which is not compliant with the ARM v7 architecture. Therefore, the count of events 0x0C and 0x0D are not accurate when using the Performance Monitor counters.

To obtain the precise count of software change of PC (0x0C) and immediate branches (0x0D), count ISB instructions alone with event 0x90 and subtract this ISB count from the events 0x0C and 0x0D results.

Solution

Impact:

Minor. The count of events 0x0C and 0x0D are not 100% precise when using the Performance Monitor counters. See Impact Details for more information.

Work-around:

Software can count ISB instructions alone with event 0x90 and subtract this ISB count from the results obtained in events 0x0C and 0x0D, to obtain the precise count of software change of PC (0x0C) and immediate branches (0x0D).

Configurations Affected:

Systems that use one or both ARM processors.

Device Revision(s) Affected: All, no plan to fix. Refer to (Xilinx Answer 47916) - Zynq-7000 Design Advisory Master Answer Record

Impact Details

The count of events 0x0C and 0x0D are not 100% precise when using the Performance Monitor counters, due to the ISB being counted in addition to the real software changes to PC (for 0x0C) and immediate branches (0x0D).

The issue also causes the corresponding PMUEVENT bits to toggle in case an ISB is executed.

PMUEVENT[13] relates to event 0x0C
PMUEVENT[14] relates to event 0x0D

AR# 47551
Date Created 05/24/2012
Last Updated 08/06/2012
Status Active
Type Design Advisory
Devices
  • Zynq-7000