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AR# 47556

Zynq-7000 AP SoC, APU - Repeated CPU Store Instructions Within Same Cache Line Can Delay Visibility Of The Store


The CPU has a Store Buffer with merging capabilities within a cache line for Normal Memory regions. The buffer continues to merge data as long as the write accesses are performed to the same cache line. The Store Buffer has a small counter to push the data out to memory after a period of time to provide external visibility of the stores. The issue is that the counter is reset each time new data is merged. If a software code sequence is looping, and continues writing data in the same cache line repeatedly, the external visibility of the written data is potentially delayed indefinitely.



Minor. This issue can create performance issues, or worst-case, a live-lock scenario, in case the external agent relies on the automatic visibility of the written data in a finite amount of time.


Insert a DMB operation after the faulty write operation in code sequences which may be affected by this erratum, in order to ensure the visibility of the written data by any external agent.

Configurations Affected:

Systems that use one or both processors.

Device Revision(s) Affected: All, no plan to fix. Refer to Zynq-7000 Device Advisory Master Answer Record

The issue can only happen on Normal Memory regions. Two example scenarios are described below, which can trigger the issue:

  • The processor keeps on incrementing a counter: writing the same word at the same address. The external agent (possibly another processor) is polling on this address, waiting for any update of the counter value to proceed. The Store Buffer will keep on merging the updated value of the counter in its cache line, so that the external agent will never see any updated value, possibly leading to live-lock.
  • The processor writes a value in a given word to indicate completion of its task; then, keeps on writing data in an adjacent word in the same cache line. The external agent keeps on polling the first word memory location to check when the processor has completed its task. The issue is the same as above, as the cache line can remain indefinitely in the merging Store Buffer, creating a possible live-lock in the system.

The recommended work-around is to insert a DMB operation after the write operation(s) continually being held in the store buffer. This is done to ensure the visibility of the written data to any external agent.  User has to insert a memory barrier, wherever he sees this issue.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47916 Zynq-7000 AP SoC Devices - Silicon Revision Differences N/A N/A
AR# 47556
Date Created 05/24/2012
Last Updated 09/17/2013
Status Active
Type Design Advisory
  • Zynq-7000
  • Zynq-7000Q
  • XA Zynq-7000