The MRC and MCR instructions are not counted in the total number of instructions passing through the Register rename pipeline stage. The values of event 0x68 and PMUEVENT[9:8] are imprecise.
Impact: |
Minor. The count of event 0x68 and PMUEVENT[9:8] are imprecise, omitting the number of MCR and MRC instructions. The inaccuracy of the total count depends on the rate of MRC and MCR instructions in the code. |
Work-around: |
No work-around is possible to achieve the functionality of counting how many instructions are precisely passing through the register rename pipeline stage when the code contains some MRC or MCR instructions. |
Configurations Affected: |
Systems that use one or both ARM processors. |
| Device Revision(s) Affected: | All, no plan to fix. Refer to Zynq-7000 Device Advisory Master Answer Record |
No work-around is possible to achieve the functionality of counting how many instructions are precisely passing through the register rename pipeline stage when the code contains some MRC or MCR instructions.