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AR# 47561 Zynq-7000, APU - The High Priority for SO and Dev Reads Feature can cause QoS Issues to Cacheable Read Transactions

Description

When the "High Priority for SO and Dev reads" feature is enabled, the L2 cache controller gives a higher priority to Strongly Ordered (SO) and Device read requests than normal cacheable reads. When the controller receives a continuous flow of SO/Device reads, the activity can prevent L2 cache line fill requests from being forwarded to the memory.

A work-around is only necessary in systems that are able to issue a continuous flow of SO or Device reads. In such a case, the work-around is to disable the "High Priority for SO and Dev reads" feature. This is the default setting in the L2 Controller.

Solution

Impact:
Trivial, refer to the Solution section for information.
Work-around:
Disable the "High Priority for SO and Dev reads" feature. This is the default setting in the L2 cache controller.
Configurations
Affected:
Systems that use one or both processors and are able to issue a continuous flow of SO or Device reads.
Device Revision(s) Affected: All, no plan to fix. Refer to Zynq-7000 Device Advisory Master Answer Record


The "High Priority for SO and Dev reads" feature can be enabled by setting bit 10 of the L2 Controller Auxiliary Control Register to 1. When enabled, this feature gives priority to Strongly Ordered and Device reads over cacheable reads in the L2 Controller AXI master interfaces. When the controller receives a continuous flow of SO or Device reads, this can prevent cacheable reads that miss in the L2 cache from being issued to memory.

This problem occurs when the following conditions are met:
  • Bit 10 (High Priority for SO and Dev reads enable) of the L2 Controller Auxiliary Control Register is set to 1.
  • The L2 Controller receives a cacheable read that misses in the L2 cache.
  • The L2 Controller receives a continuous flow of SO or Device reads that take all address slots in the master interface.

Impact Details: When the conditions above are met, the line-fill resulting from the L2 cache miss is not issued till the flow of SO/Device reads stops. Note that each L2 Controller master interface has four address slots, so that the Quality of Service issue only appears on the cacheable read if the L1 is able to issue at least four outstanding SO/Device reads.

Actions

AR# 47561
Date Created 05/24/2012
Last Updated 08/06/2012
Status Active
Type Design Advisory
Devices
  • Zynq-7000
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