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AR# 47561

Zynq-7000 AP SoC, APU - The high priority for SO and Dev Reads feature might cause QoS issues to cacheable read transactions

Description

When the "High Priority for Strongly Ordered (SO) and Device (Dev) reads" feature is enabled, the L2 cache controller gives a higher priority to SO and Dev read requests than normal cacheable reads. When the controller receives a continuous flow of SO/Device reads, the activity might prevent L2 cache line fill requests from being forwarded to the memory.

A work-around is only necessary in systems that are able to issue a continuous flow of SO or Dev reads. In such a case, the work-around is to disable the "High Priority for SO and Dev reads" feature. This is the default setting in the L2 Controller.

Solution

Impact: Trivial.
Work-around: Disable the "High Priority for SO and Dev reads" feature. This is the default setting in the L2 cache controller.
Configurations
Affected:
Systems that use one or both processors and are able to issue a continuous flow of SO or Dev reads.
Device Revision(s) Affected: All, no plan to fix. Refer to (Xilinx Answer 47916) Zynq-7000 AP SoC Silicon Revision Differences.


The "High Priority for SO and Dev reads" feature can be enabled by setting bit 10 of the L2 Controller Auxiliary Control Register to 1. When enabled, this feature gives priority to Strongly Ordered and Device reads over cacheable reads in the L2 Controller AXI master interfaces. When the controller receives a continuous flow of SO or Dev reads, this can prevent cacheable reads that miss in the L2 cache from being issued to memory.

This problem occurs when the following conditions are met:

  • Bit 10 (High Priority for SO and Dev reads enable) of the L2 Controller Auxiliary Control Register is set to 1.
  • The L2 Controller receives a cacheable read that misses in the L2 cache.
  • The L2 Controller receives a continuous flow of SO or Device reads that take all address slots in the master interface.

Impact Details: When the conditions above are met, the line-fill resulting from the L2 cache miss is not issued till the flow of SO/Dev reads stops. Note that each L2 Controller master interface has four address slots, so that the Quality of Service issue only appears on the cacheable read if the L1 is able to issue at least four outstanding SO/Dev reads.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47916 Zynq-7000 AP SoC Devices - Silicon Revision Differences N/A N/A
AR# 47561
Date Created 05/24/2012
Last Updated 04/11/2013
Status Active
Type Design Advisory
Devices
  • Zynq-7000
  • XA Zynq-7000