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AR# 47562

Zynq-7000, APU - A Continuous Write Flow can Stall a Read Targeting the Same Memory Area

Description

When a read (cacheable or not) with Normal Memory attributes is received by the L2 cache controller, hazard checking is performed on the read with the active writes in the store buffer. If an address match is detected, the read is stalled until the write completes. However, a continuous flow of writes can stall a read targeting the same memory area.

This issue does not lead to data corruption and normal software code is not expected to contain long write sequences.

Solution

Impact:
Trivial. When the conditions above are met, the read might be stalled till the write flow stops. Note that this issue does not lead to any data corruption. Furthermore, normal software code is not expected to contain long write sequence like the one causing this issue.
Work-around:
There is no work-around for this issue and none is expected to be necessary.
Configurations
Affected:
Systems that use one or both ARM processors.
Device Revision(s) Affected: All, no plan to fix. Refer to Zynq-7000 Device Advisory Master Answer Record

When a read (cacheable or not) with Normal Memory attributes is received by the L2 Controller, hazard checking is performed on the read with the active writes in the store buffer. If an address match is detected, the read is stalled until the write completes. Due to this issue, a continuous flow of writes can stall a read targeting the same memory area.

This problem occurs when the following conditions are met:
  • L2 Controller receives continuous write traffic targeting the same address and with Normal Memory attributes.
  • L2 Controller receives a read targeting the same 32-byte memory area as the writes.
AR# 47562
Date Created 05/24/2012
Last Updated 08/06/2012
Status Active
Type Design Advisory
Devices
  • Zynq-7000