We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 47564

Zynq-7000 AP SoC, DDR - I/O Buffers do not Support External VREF


DDR I/O buffers (DDRIOB) use differential input receivers for which one input to the receiver is connected to the data input and the other is connected to a voltage reference pin called VREF (set to half of the DDR VCC I/O voltage).

VREF needs to be supplied from the internal voltage source because the external VREF feature for DDRIOB is not supported.


Minor. Use the internal VREF reference.
Use the internal VREF reference, see the Solution section for more information.
Systems that use the PS DDR memory controller.
Device Revision(s) Affected: Refer to Zynq-7000 Device Advisory Master Answer Record
Use the Internal VREF feature. To enable internal VREF:
  • Set DDRIOB_DDR_CTRL.VREF_EXT_EN to 00 (disconnect I/Os from external signal)
  • Set DDRIOB_DDR_CTRL.VREF_SEL to the appropriate voltage setting depending on the DDR standard. (VREF = Vcco_ddr / 2)
  • Set DDRIOB_DDR_CTRL.VREF_INT_EN to 1 to enable the internal VREF generator
AR# 47564
Date Created 05/24/2012
Last Updated 11/12/2012
Status Active
Type Design Advisory
  • Zynq-7000