The data I/O buses of NAND, NOR, and Quad-SPI devices on the MIO pins are left floating by the BootROM, leading to higher power consumption. In non-secure boot modes, the work-around is to enable the weak internal pull-up resistors on the MIO pins during the boot process.
Impact: Trivial. There is no functional impact to the user.
Work-around: Enable internal pull-ups by writing to the slcr.PIN_MUX_xx registers during the boot process by creating set commands in an .INT file and link it into the Boot Image using BootGen. Refer the Software Developers Guide for information on the .INT file syntax and BootGen procedures.
Configurations Affected: All.
Device Revision(s) Affected: Refer to (Xilinx Answer 47916) - Zynq-7000 Design Advisory Master Answer Record
Enable internal pull-ups by writing to the slcr.PIN_MUX_xx registers during the boot process by creating set commands in an .INT file and link it into the Boot Image using BootGen. Refer the Software Developers Guide for information on the .INT file syntax and BootGen procedures.
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 52538 | Zynq-7000 AP SoC - Boot and Configuration | N/A | N/A |