When operating the SPI interface in master mode the setup timing for MI is dependent on the SPI reference clock period. It is always equal to one reference clock period.
| Impact: | Trivial. Satisfying the new setup requirements guarantees not to have issues. |
| Work-around: | As long as the reference clock values are known before designing the board and timing is met with respect to a setup equal to the period of the slowest possible reference clock, there is not going to be any issues. |
| Configurations Affected: | Systems that use the SPI controller in master mode. |
| Device Revision(s) Affected: | Refer to Zynq-7000 Device Advisory Master Answer Record |