The setup timing for MI is dependent on the SPI reference clock period when operating the SPI interface in master mode. It is always equal to one reference clock period.
|Trivial. Satisfying the new setup requirements guarantees not to have issues.|
|Work-around:||As long as the reference clock values are known before designing the board and timing is met with respect to a setup equal to the period of the slowest possible reference clock, there is not going to be any issues.|
|Configurations Affected:||Systems that use the SPI controller in master mode.|
|Device Revision(s) Affected:||Refer to (Xilinx Answer 47916) - Zynq-7000 AP SoC Silicon Revision Differences|
The SPI_REF_CLK clock frequency must be greater than the CPU_1x clock frequency.
For GES devices, the SPI_REF_CLK clock frequency must be less than or equal 125 MHz.
For Production devices, the SPI_REF_CLK clock frequency must be less than or equal 200 MHz.
Ensure that your final design meets these constraints.