We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 47580

Zynq-7000 AP SoC, DDR - LPDDR2 Per-Bank Refresh Is Not Supported


The LPDDR2 per-bank refresh function is not supported.





The work-arounds are explained below.

Configurations Affected:

Systems that use the DDR memory controller in LPDDR2 mode with eight banks.

Device Revision(s) Affected: All. No plan to fix. Refer to (Xilinx Answer 47916) - Zynq-7000 AP SoC Silicon Revision Differences.


The best overall work-around is to avoid using per-bank refresh, and to use all-bank refresh instead (i.e., set reg_ddrc_per_bank_refresh = 0).

If this is not acceptable, the individual issues can be worked around as follows:

  • For the duration of initialization, set reg_ddrc_t_rfc_min to the value appropriate for all-bank refreshes. When initialization is complete (detected by monitoring ddrc_reg_operating_mode), this can be changed to the value appropriate for per-bank refreshes.
  • Avoid high priority activates by programming the CAM to be a single priority. This can be done by setting reg_ddrc_lpr_num_entries to 31.
  • Avoid accessing mode registers when auto-refresh is enabled reg_ddrc_dis_auto_refresh must be set to 1 when performing MRW or MRR. Also, automatic temperature derating must be disabled in order to prevent automatic MRRs from being executed; reg_ddrc_derate_enable must be set to 0.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47916 Zynq-7000 AP SoC Devices - Silicon Revision Differences N/A N/A
AR# 47580
Date Created 05/24/2012
Last Updated 11/07/2013
Status Active
Type Design Advisory
  • Zynq-7000
  • XA Zynq-7000
  • Zynq-7000Q