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AR# 47585

Zynq-7000 AP SoC, APU - Visibility of Debug Enable Access Rights to Enable/Disable Tracing is not Ensured by an ISB Instruction

Description

Although visibility is correctly achieved for all debug-related features, the ISB instruction is not sufficient to make the Authentication Status Register changes visible to the trace flow. As a consequence, the trace stops with the current waypoint up to the next exception entry or return, or to the next serial branch, even when an ISB is executed.

To work around the issue, the ISB instruction must be replaced by one of the events causing the change to be visible. In particular, replacing the ISB by a MOVS PC to the next instruction achieves the correct functionality.

Solution

Impact:

Minor, trace flow might not start, nor stop, as expected by the program.

Work-around:

Place the ISB instruction by one of the events causing the change to be visible. In particular, replacing the ISB by a MOVS PC to the next instruction will achieve the correct functionality.

Configurations Affected:

Systems that use the Trace feature of an ARM processor.

Device Revision(s) Affected: All, no plan to fix. Refer to (Xilinx Answer 47916) Zynq-7000 Design Advisory Master Answer Record


According to the ARM architecture, any change in the Authentication Status Register should be made visible to the processor after an exception entry or return, or an ISB instruction.

Although this is correctly achieved for all debug-related features, the ISB is not sufficient to make the changes visible to the trace flow. As a consequence, the trace will stop with the current waypoint up to the next exception entry or return, or to the next serial branch, even when an ISB is executed.

A serial branch is one of the following:

Data processing to PC with the S bit set (for example, MOVS pc, r14)
LDM pc ^

AR# 47585
Date Created 05/24/2012
Last Updated 10/16/2012
Status Active
Type Design Advisory
Devices
  • Zynq-7000