With dynamic branch prediction enabled, the CPU reports parity errors occurring on the BTAC and GHB RAMs. This reporting is done even when the parity error detection mechanism for the RAM is disabled.
Parity error detection is usually enabled. A work-around, if needed, is to enable parity error detection prior to enabling the dynamic branch prediction. In systems where branch prediction is enabled while parity error detection remains disabled, the work-around is to ignore any parity issues.
| Impact: | Minor |
Work-around: |
Enable parity error detection prior to enabling branch prediction, refer to the Work-around Details section, below, for more information. |
Configurations Affected: |
Systems that use one or both processors with dynamic branch prediction and parity. |
| Device Revision(s) Affected: | All, no plan to fix. Refer to (Xilinx Answer 47916) -Zynq-7000 Device Advisory Master Answer Record. |
In Cortex-A9, when dynamic branch prediction is enabled (Cortex-A9 architecture register:SCTLR[11] = 1), the processor is expected to report parity errors occurring on the BTAC and GHB RAMs, when the parity error detection logic is enabled (Cortex-A9 ACTLR[9]= 1). However, any parity error on the BTAC or GHB RAM will be reported even when parity error detection is not enabled.
Impact Details
Due to this issue, unexpected parity errors may be reported when parity is not enabled if any parity error happens on the BTAC or GHB RAMs. The issue is not expected to cause any significant impact because parity is likely to be enabled very soon in the boot process.
Work-around Details
Since parity errors on the BTAC and GHB RAMs are not reported when the dynamic branch prediction is not enabled, the work-around consists of enabling parity error detection (ACTLR[9] = 1) prior to enabling the dynamic branch prediction (SCTLR[11] = 1). In systems where branch prediction is enabled while parity error detection remains disabled, the work-around is to ignore any parity issues.