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AR# 47589

Zynq-7000 AP SoC, Signals - Programming GPIOB to HSTL18 when VCCO_MIO is at 2.5/3.3V can damage IOB receiver


I/O buffers for MIO pins (GPIOBs) must not be programmed to use VREF (for differential HSTL receivers) if VCCO_MIO is 2.5V or 3.3V. Long term damage can occur to the I/O buffer if the following conditions are true:

  1. At least one I/O of a particular bank is setup as LVCMOS25, LVCMOS33 or LVTTL using the slcr.MIO_PIN_*[IO_Type] control bit.
  2. Internal VREF voltage is enabled using slcr.GPIOB_CTRL[VREF_SW_EN] register control bit and VREF pin is set to 0.9V.
  3. One I/O (in the same bank as the IO from #1) is configured as HSTL18 with output tristated and pad driven to 2.5V or higher level.


GPIOBs must not be programmed as VREF for differential receivers if VCCO_MIO is 2.5V or 3.3V.

AR# 47589
Date Created 04/27/2012
Last Updated 06/05/2013
Status Active
Type General Article
  • Zynq-7000
  • Zynq-7000Q
  • XA Zynq-7000