We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 47596

Zynq-7000 AP SoC, Boot - Quad-SPI controller, in non-Quad-SPI boot mode, does not drive HOLD_B inactive during SPI data phase


When boot modeJTAG, NORorNANDis selected, the Quad-SPI HOLD_B pin is held low and the controller cannot communicate with the Quad-SPI device. This is because MIO pin 5 (part of the Boot_Mode select) is strapped low.

When other boot modes are selected,MIO pin 5 is strapped high and there are no issues.


Do not use a Quad-SPI device in the system when JTAG, NOR or NAND is the boot device.

The Quad-SPI devices have a dual-purpose pin: HOLD_B/DQ3. An active lowHOLD_B gates CLK and DIN and tri-states DOUT when CS_B is active. HOLD_B/DQ3 is mapped to MIO pin 5 which is pulled high when Quad-SPI boot mode is selected. In this case, the Quad-SPI works as expected. However, certain boot modes, such as JTAG, pull MIO[5] low. If QSPI is used in these other boot modes, it leads to the assertion of HOLD_B in certain Quad-SPI protocol phases, which will hang the Quad-SPI transaction.

Minor. Only in rare cases is it desireable to include aQuad-SPI device and not boot from it.
Attacha Quad-SPI device only when it is the boot device.
Configurations Affected:
Systems that use the Quad-SPI interface, but don't boot in Quad-SPI mode.
Device Revision(s) Affected: Refer to Zynq-7000 Device Advisory Master Answer Record

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
52538 Zynq-7000 AP SoC - Boot and Configuration N/A N/A

Associated Answer Records

AR# 47596
Date Created 09/05/2012
Last Updated 03/07/2013
Status Active
Type Design Advisory
  • Zynq-7000