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AR# 47606

Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 (ISE 14.1 / Vivado 2012.1) - ECRC support in IES Silicon


Version Found: v1.1
Version Resolved and other Known Issues: See (Xilinx Answer 47441)

The Virtex-7 FPGA Integrated Block For PCI Express v1.1 core does not support ECRCin IES Silicon.


The End-to-End CRC (ECRC) feature cannot be enabled on a per function basis for users targeting IES silicon. The ECRC capability must be enabled or disabled identically for all enabled functions. This restriction applies to users targeting IES silicon.This is a known issue and will be fixed in a future release of the core.

NOTE: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
05/08/2012 - Initial release

Linked Answer Records

Master Answer Records

AR# 47606
Date Created 05/04/2012
Last Updated 05/20/2012
Status Active
Type Known Issues
  • Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)