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AR# 47608

Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 (ISE 14.1 / Vivado 2012.1) - PF0_PM_CSR_NOSOFTRESET must be tied to 1'b1 in IES Silicon

Description

Version Found: v1.1
Version Resolved and other Known Issues: See (Xilinx Answer 47441)

Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 corerequires PF0_PM_CSR_NOSOFTRESET to be tied to 1'b1 in IES Silicon.

Solution

The generated core files default the value toPF0_PM_CSR_NOSOFTRESET1'b1. Users targeting IES silicon should not change this setting from the default value.This is a known issue and will be fixed in a future release of the core.

NOTE: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
05/08/2012 - Initial release

Linked Answer Records

Master Answer Records

AR# 47608
Date Created 05/04/2012
Last Updated 05/20/2012
Status Active
Type Known Issues
IP
  • Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)