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AR# 47615 Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 (ISE 14.1 / Vivado 2012.1) - Timing Violations in Certain IP Configurations

Description

Version Found: v1.1
Version Resolved and other Known Issues: See (Xilinx Answer 47441)

There are certain IP configurations thatdo not meet timing.

Solution

This is a known issue and will be fixed in a future release of the core. If you run into timing violations with implementation of the default core generation, please create a WebCase with Xilinx Technical Support and submit the XCO file and the timing report.

NOTE: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.


Revision History
05/08/2012 - Initial release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47441 Virtex-7 FPGA Gen3 Integrated Block for PCI Express - Release Notes and Known Issues for All Versions N/A N/A

Actions

AR# 47615
Date Created 06/28/2012
Last Updated 07/16/2012
Status Active
Type Known Issues
IP
  • Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)
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