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AR# 47620

Clocking Wizard v3.5 - Release Notes and Known Issues


This Release Note is for the Clocking Wizard v3.5 released in ISE Design Suite14.1 and contains the following:

  • General Information
  • New Features
  • Bug Fixes
  • Known Issues


General Information

The Clocking Wizard v3.5 supports the 7 series and Zynq FPGAs.

New Features in v3.5

There are no new features in this version of the Wizard.

Bug Fixes in v3.5

Clocking Wizard v3.3 incorrectly lists the Spartan-6 Low Power Devices as pre-production.

Clocking Wizard v3.3,the Defense Grade Virtex-6Q Lower Power devices are not supported. For more information, see (Xilinx Answer 42530).

Known Issues

In v3.5 of the Clocking Wizard, if you select a BUFHCE as the output buffer the example design might be unroutable with the default constraints. The BUFHCE can drive a single clock region.

In the Clocking Wizard v3.5, example design implementation with the BUFHCE as the output buffer might fail due to the placement of logic in multiple clock regions. To work around the issue,you can provide constraints to lock the output clock pin and the BUFHCE into the same bank.
AR# 47620
Date Created 05/02/2012
Last Updated 07/09/2012
Status Active
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6Q
  • Virtex-6QL
  • Virtex-7
  • Virtex-7 HT
  • Artix-7
  • Kintex-7
  • Spartan-6 LX
  • Spartan-6 LXT
  • Spartan-6Q
  • Less