This Release Note is for the SelectIO Wizard v4.1 released in ISE Design Suite 14.2, and the XADC Wizard v4.2 released in Vivado 2012.2 tools which contain the following information:
The SelectIO Wizard v4.1/v4.2 supports the 7 series FPGAs, Zynq, Virtex-6, and Spartan-6 device families. The Wizard is used to simplify the integration of the SelectIO technology in designs.
New Features in v4.1 and v4.2
There are no new features in this revision of the Wizard.
Bug Fixes in v4.1
In v3.3 of the SelectIO Wizard, Defense Grade Virtex-6Q Lower Power devices are not supported. For more information, see (Xilinx Answer 42529).
Bug Fixes in v4.2
There are no bug fixes in v4.2.
Known Issues in 4.1
In the SelectIO Wizard v4.1 example design, there are timing violations and failures detected in timing simulation for a bidirectional bus. The example design testbench provides a delay for the loopback data, but this delay cannot be provided on the bidirectional bus. The timing simulation of SelectIO Wizard testbench fails.
Known Issues in 4.2
The following error can occur if running implementation on the example design due to the clock domain crossing of "equal" signal used in the example design for data validation:
In Vivado 2012.3 SelectIO Wizard v4.2 example designs are failing for more than 8:1 serialization factor. The placer is unable to place IBUF for ISERDES and OBUF for OSERDES. The work-around is to implement the design in ISE.