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AR# 47644

XAUI v10.3 and later (ISE) - Timing failures may be seen with the 7 Series FPGA Example Design

Description

Timing failures may be seen with the XAUI core Example Design when targeting 7 series devices.

Solution

The example design has low device utilization and a low utilization window is created, but sometime timing cannot be met if the core is constrained to this window, as it needs to be placed close to the GTs. The timing failures should not be seen in larger designs where the low utilization window would not get set. To work around this issue and disable the low device utilization window, the following environment variable can be set:

% setenv PAR_USE_LOWUTILHEUR 0

Alternatively an area group can be added to the UCF:

AREA_GROUP "xaui_core" RANGE = "CLOCKREGION_XiYj:CLOCKREGION_XiYj";
INST "xaui_block/*" AREA_GROUP = "xaui_core";

Where "i" and "j" are integers that constrain the clock region to be next to the chosen transceivers.


AR# 47644
Date Created 05/01/2012
Last Updated 12/15/2012
Status Active
Type General Article
Tools
  • ISE Design Suite - 14.1
IP
  • XAUI