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AR# 47664

13.4 Virtex-6 Route - Incorrect routing of BUFIODQS clock nets possible

Description

Cases have been seen where BUFIODQS clock nets have not been routed when using the OPTDELAY resource.

This is required to match the delay of associated BUFR clocks when both are clocking the same I/O components.

There are two known causes:

  1. If PAR is run with multi-threading enabled (-mt) the multi-threaded router does not respected the locked route previously done by PAR using the OPTDELAY resource.
    The multi-threaded router will only rip up and reroute the net if it is involved in a failing timing constraint (maxskew in one case).
     
  2. If the net is unrouted and then rerouted in FPGA Editor it will not be rerouted with the necessary OPTDELAY resource.

Correct routing of BUFDQS net using the OPTDELAY resource:

bufiodqs.png




Solution

A DRC check will be created to catch incorrectly routed BUFIODQS nets.

Meanwhile the design can be examined in FPGA Editor if incorrect routing is suspected.

Remove any unnecessary timing constraints to prevent the rip up and reroute behavior mentioned above.

AR# 47664
Date Created 04/30/2012
Last Updated 03/23/2015
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6Q
  • Virtex-6QL
  • Less
Tools
  • ISE Design Suite - 13
  • ISE Design Suite - 13.1
  • ISE Design Suite - 13.2
  • More
  • ISE Design Suite - 13.3
  • ISE Design Suite - 13.4
  • Less