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AR# 47671

Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 (ISE 14.1 / Vivado 2012.1) - Incorrect reset of ARI Capable Hierarchy bit in the SR-IOV control register

Description

Version Found: v1.1
Version Resolved and other Known Issues: See (Xilinx Answer 47441)

The ARI Capable Hierarchy bit in the SR-IOV control register is incorrectly reset by a function level reset of the physical function.

Solution

This is a known issue to be fixed in a future release of the core.

NOTE: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
05/08/2012 - Initial release

Linked Answer Records

Master Answer Records

AR# 47671
Date Created 05/04/2012
Last Updated 05/20/2012
Status Active
Type Known Issues
IP
  • Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)