^
Advanced Search

AR# 47688 7 Series FPGA GTP Transceiver - Implementation error in ISE 14.1/Vivado 2012.1 software when sharing reference clocks

Description


If generating GTP transceiver designs in both ISE 14.1 and Vivado 2012.1 software flows, an implementation error occurs.

How do I work around this?

Solution


The following error occurs during implementation for 7 series GTP designs in ISE 14.1 and Vivado 2012.1:

"ERROR:Place:1390 - Unroutable Placement! A GTPE_COMMON / GT clock component pair have been found that are not placed at a routable site pair."

This error occurs when a reference clock is shared between the East and West Quads.

To work around this issue, use the reference clock of the same quad. This is expected to be fixed in ISE Design Suite 14.2 and Vivado Design Suite 2012.2.

Actions

AR# 47688
Date Created 05/02/2012
Last Updated 05/02/2012
Status Active
Type
Devices
  • Artix-7
Tools
  • ISE Design Suite - 14.1
  • Vivado - 2012.1
Feed Back