UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 47702

LogiCORE IP Aurora 8B10B v8.1 (AXI4-stream) (ISE 14.1/Vivado 2012.1) - Release Notes and Known Issues

Description

This answer record contains the Release Notes for the Aurora 8B/10B v8.1 Core, released in the ISE 14.1 and Vivado 2012.1 design tools, and includes the following:

  • New Features
  • Supported Devices
  • Resolved Issues
  • Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide.

Solution

New Features

ISE Design Suite:

  • ISE 14.1 design tools support
  • Virtex-7 and Kintex-7 GES silicon support
  • Scrambler/Descrambler support

Vivado Design Suite:

  • 2012.1 design tools support
  • Virtex-7 and Kintex-7 GES silicon support
  • Scrambler/Descrambler support

Supported Devices

ISE Design Suite:

  • Virtex-7
  • Virtex-7 XT
  • Virtex-7 Low Voltage (-2L)
  • Defense Grade Virtex-7Q (XQ)
  • Defense Grade Virtex-7Q Low Voltage (XQ,-2L)
  • Kintex-7
  • Kintex-7 Low Voltage (-2L)
  • Defense Grade Kintex-7Q (XQ)
  • Defense Grade Kintex-7Q Low Voltage (XQ,-2L)
  • Virtex-6CXT/LXT/SXT/HXT
  • Virtex-6 Lower Power (-1L)LXT/SXT
  • Defense Grade Virtex-6Q(XQ)LXT/SXT
  • Defense Grade Virtex-6Q Lower Power(XQ,-1L) LXT/SXT
  • Spartan-6LXT
  • Automotive Spartan-6LXT
  • Defense Grade Spartan-6Q LXT

Vivado Design Suite:

  • Virtex-7
  • Virtex-7 XT
  • Virtex-7 Low Voltage (-2L)
  • Defense Grade Virtex-7Q (XQ)
  • Defense Grade Virtex-7Q Low Voltage (XQ,-2L)
  • Kintex-7
  • Kintex-7 Low Voltage (-2L)
  • Defense Grade Kintex-7Q (XQ)
  • Defense Grade Kintex-7Q Low Voltage (XQ,-2L)

Resolved Issues

ISE Design Suite:

  • Add support for xc7vx485tl device
  • Provide constraints for xc7k325t-ffg900 on KC724 board
  • Maximum allowed 7 series GTX reference clock frequency increased from 670 MHz to 700 MHz in -3 devices
  • 13.3 - Aurora 8b10b v7.1 - GT Reset Requirement is not followed
  • ISE 13.3 - Aurora 8b10b v 7.1 - UG766 - GSR_DONE_IN signal is not documented
  • aurora_8b10b_7.1: 14.1_1218: Coregen_IP_Deliverables structure mismatch

Vivado Design Suite:

  • Add support for xc7vx485tl device
  • Provide constraints for xc7k325t-ffg900 on KC724 board
  • Maximum allowed 7 series GTX reference clock frequency increased from 670 MHz to 700 MHz in -3 devices
  • 13.3 - Aurora 8b10b v7.1 - GT Reset Requirement is not followed
  • ISE 13.3 - Aurora 8b10b v 7.1 - UG766 - GSR_DONE_IN signal is not documented
  • aurora_8b10b_7.1: 14.1_1218: Coregen_IP_Deliverables structure mismatch

Known Issues

There are no known issues for v8.1 of this core at time of release with ISE 14.1 and Vivado 2012.1 design tools.

The most recent information including known issues, work-arounds, and resolutions for this version is provided in the IP Release Notes Guide located at: http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf

AR# 47702
Date Created 05/04/2012
Last Updated 11/26/2014
Status Active
Type Release Notes
IP
  • Aurora 8B/10B
Boards & Kits
  • Kintex-7 FPGA KC724 Characterization Kit