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AR# 47704

LogiCORE IP Aurora 64B66B v7.1 - ISE 14.1/Vivado 2012.1 - Release Notes and Known Issues

Description

This answer record contains the Release Notes for the Aurora64B66B v7.1 Core, released in theISE 14.1 and Vivado 2012.1 design tools, and includes the following:

  • New Features
  • Supported Devices
  • Resolved Issues
  • Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide.

Solution

NewFeatures

ISE Design Suite:

  • ISE 14.1 design tools support
  • Virtex-7, Kintex-7 GES silicon support
  • Virtex-7 GTH silicon support
  • Divide by 2and 8 line rate support for Virtex-6 FPGA GTH
  • AXI4 Lite DRP interface to user
  • CRC32 option for framing user interface
  • Usage of BUFG optimized

Vivado Design Suite:

  • 2012.1 design tools support
  • Virtex-7, Kintex-7 GES silicon support
  • Virtex-7 GTH silicon support
  • Divide by 2and 8 line rate support for Virtex-6 FPGA GTH
  • AXI4 Lite DRP interface to user
  • CRC32 option for framing user interface
  • Usage of BUFG optimized

Supported Devices

ISE Design Suite:

  • Virtex-7
  • Virtex-7 XT
  • Virtex-7 HT
  • Virtex-7 Low Voltage (-2L)
  • Defense Grade Virtex-7Q (XQ)
  • Defense Grade Virtex-7Q Low Voltage (XQ,-2L)
  • Kintex-7
  • Kintex-7 Low Voltage (-2L)
  • Defense Grade Kintex-7Q (XQ)
  • Defense Grade Kintex-7Q Low Voltage (XQ,-2L)
  • Virtex-6 XC LXT/SXT/HXT
  • Virtex-6 XQ LXT/SXT
  • Virtex-6 -1L XC LXT/SXT

Vivado Design Suite:

  • Virtex-7
  • Virtex-7 XT
  • Virtex-7 HT
  • Virtex-7 Low Voltage (-2L)
  • Defense Grade Virtex-7Q (XQ)
  • Defense Grade Virtex-7Q Low Voltage (XQ,-2L)
  • Kintex-7
  • Kintex-7 Low Voltage (-2L)
  • Defense Grade Kintex-7Q (XQ)
  • Defense Grade Kintex-7Q Low Voltage (XQ,-2L)

Resolved Issues

ISE Design Suite:

  • Maximum allowed 7-Series GTX reference clock frequency increased from 670 MHz to 700 MHz in -3 devices
  • Add GTH support for 7-Series
  • Add /8and /2 line rate support for Virtex-6 FPGA GTH
  • Remove GSR_DONE signal from reset logic
  • Add support for Virtex-7 HT devices
  • Add support for Virtex-7Q and Kintex-7Q devices
  • Virtex-7 - xc7vx485t - ffg1761 - one quad missing in wizard
  • Generated veo/vho file is missing port definition
  • Lower the usage of BUFGs in the core

Vivado Design Suite:

  • Maximum allowed 7 series FPGAs GTX reference clock frequency increased from 670 MHz to 700 MHz in -3 devices
  • Add GTH support for 7 series FPGAs
  • Add /8and /2 line rate support for Virtex-6 FPGA GTH
  • Remove GSR_DONE signal from reset logic
  • Add support for Virtex-7 HT devices
  • Add support for Virtex-7Q and Kintex-7Q devices
  • Virtex-7 - xc7vx485t - ffg1761 - one quad missing in wizard
  • Generated veo/vho file is missing port definition
  • Lower the usage of BUFGs in the core

Known Issues

ISE Design Suite:

  • Virtex-6 HXT/GTH selection of quads should be consecutive
    Description: In Virtex-6 HXT/GTH, for line rates >9.8G the quad selection should be consecutive
    There cannot be a unused quad between two used quads
  • Virtex-6 HXT/GTH ES/PS attribute settings
    Description: Refer Aurora 64B66B v5.1 for ES settings for GTH transceivers
    Refer Aurora 64B66B v6.1 for PS settings for GTH transceivers
  • AXI4_LITE based DRP interface is not fully AXI4_LITE compliant
    Description: AXI4_LITE to DRP is port mapped and is not native AXI4_LITE

Vivado Design Suite:

  • AXI4_LITE based DRP interface is not fully AXI4_LITE compliant
    Description: AXI4_LITE to DRP is port mapped and is not native AXI4_LITE

The most recent information, including known issues, work-arounds, and resolutions for this version is provided in the IP Release Notes Guide located at: http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf

AR# 47704
Date Created 05/04/2012
Last Updated 05/16/2012
Status Active
Type Release Notes
IP
  • Aurora 64B/66B