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AR# 47719

2012.x IP Packager - "ERROR:sim - Line ##: Formal has no actual or default value"


I have packaged an IP to target both Vivado and CORE Generator design tool flows.

However, when an IP core is generated in the CORE Generator tool, an error occurs for several ports. 

The ports reported in the error messages were disabled for the core I generated.

Below is an example error message when generating the packaged IP in the CORE Generator tool:

Customize and GenerateINFO:sim:172 - Generating IP...
Applying current project options...
Finished applying current project options.
Resolving generics for 'my_core_v1_0_0'...
Applying external generics to'my_core_v1_0_0'...
Delivering associated files for'my_core_v1_0_0'...
Generating implementation netlist for'my_core_v1_0_0'...
INFO:sim - Pre-processing HDL files for'my_core_v1_0_0'...
Running synthesis for'my_core_v1_0_0'

ERROR:sim - "/project/tmp/_cg/my_core_top.vhd" Line 62: Formal <reset> has no actual or default value.
ERROR:sim -"/project/tmp/_cg/my_core_top.vhd" Line 65: Formal <data2>has no actual or default value.
ERROR:sim - Failed executing Tcl generator.
Closed project file.


The IP Packager in Vivado Design Suite 2012.x allows you to apply constant drivers to top-level input ports based on the interface parameters.

If an IP is packaged to use this feature and the generated core does not used that particular pin (requiring the default, constant driver), generation will fail with the error above.

The core can be correctly generated in the Vivado design tools.

To work around this issue in Vivado Design Suite 2012.x, package the IP separately for Vivado and CORE Generator tools, or do not to use the default driver feature.

AR# 47719
Date Created 05/03/2012
Last Updated 06/11/2014
Status Active
Type Known Issues
  • Vivado Design Suite - 2012.1
  • Vivado Design Suite - 2012.2