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AR# 47736

Block Memory Generator v7.1 - ISE 14.1/VIVADO 2012.1- Release Notes and Known Issues

Description

This Release Notes and Known Issues Answer Record is for theBlock Memory Generator v7.1 Core, released in ISE 14.1 software and contains the following information:

This Article contains the following sections:

1. Introduction
2. New Features
2.1 ISE
2.2 Vivado
3. Supported Devices
3.1 ISE
3.2 Vivado
4. Resolved Issues
4.1 ISE
4.2 Vivado
5. Known Issues
5.1 ISE
5.2 Vivado
6. Technical Support

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

Solution

1. INTRODUCTION

For installation instructions, general CORE Generator known issues and design tools requirements, see the IP Release Notes Guide at:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

For the most recent updates to the IP installation instructions for this core, please go to:
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm

For system requirements:
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm

This file contains release notes for the Xilinx LogiCORE IP Block Memory Generator v7.1 solution. For the latest core updates, see the product page at: http://www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm.

................................................................................

2. NEW FEATURES

2.1 ISE
- ISE 14.1 software support
- Defense Grade Virtex-7Q, Kintex-7Q, Artix-7Q and Zynq-Q, Defense Grade Lower Power Kintex-7QL and Artix-7QL, and Automotive Zynq device support

2.2 Vivado
- 2012.1 software support
- Defense Grade Virtex-7Q, Kintex-7Q, Artix-7Q and Zynq-Q, Defense Grade Lower Power Kintex-7QL and Artix-7QL, and Automotive Zynq device support

................................................................................

3. SUPPORTED DEVICES

3.1 ISE

The following device families are supported by the core for this release.

All 7 Series devices
Zynq-7000 devices
All Virtex-6 devices
All Spartan-6 devices
All Virtex-5 devices
All Spartan-3 devices
All Virtex-4 devices

3.2 Vivado
All 7 Series devices
Zynq-7000 devices

................................................................................

4. RESOLVED ISSUES

The following issues are resolved in Block Memory Generator v7.1:
4.1 ISE
-NA

4.2 Vivado
-NA

................................................................................

5. KNOWN ISSUES

5.1 ISE

The following are known issues for v7.1 of this core at time of release:

1. Virtex-6 and Spartan-6: BRAM Memory collision error, when the user selects TDP (write_mode= Read First)
Work around: The user must review the possible scenarios that cause the collision and revise their design to avoid those situations.
- CR588505

Note: Refer to UG383, 'Conflict Avoidance' section when using TDP Memory - with
Write Mode = Read First in conjunction with asynchronous clocking

2. Power estimation figures in the data sheet are preliminary for Virtex-5 and Spartan-3.

3. Core does not generate for large memories. Depending on the machine the ISE CORE Generator software runs on, the maximum size of the memory that can be generated will vary. For example, a Dual Pentium-4 server with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes

- CR 415768
- AR 24034

5.2 Vivado
-NA

Technical Support

To obtain technical support, create a WebCase at www.xilinx.com/support. Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used according to the guidelines described in the core documentation, and cannot guarantee timing, functionality, or support of this product for designs that do not follow specified guidelines.

AR# 47736
Date Created 05/08/2012
Last Updated 05/16/2012
Status Active
Type Release Notes
Tools
  • ISE Design Suite - 14.1
  • Vivado - 2012.1
IP
  • Block Memory Generator