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AR# 47762

MIG 7 Series DDR3 - Data Offset Usage

Description

The MIG 7 series design's PHY Control Block uses a data offset value for all read, write, and non-data commands. The calibration algorithm calculates the read data offset for each bank containing a data group during the DQSFOUND calibration stage, while the write offset is determined based on memory and design parameters. This answer record details how the data offsets are determined and what the associated signals are.

Solution

During DQSFOUND calibration, the PHY determines the read data offset (time between read command and valid read data) for each bank containing a data group. The values found during this stage are used by the PHY during the remaining calibration stages and are sent by the calibration logic to the PHY on the calib_data_offset_0/1/2 signals.The calib_data_offset_0 signal is always used and calib_data_offset_1/2 are used when the memory interface is contained in 2/3 banks. After calibration completes, the memory controller sends mc_data_offset/_1/_2 to the PHY when 1, 2, or 3 banks are used. Each bank may have different data offset values. The separate values are used for each bank's PHY Control Block's Data Offset field.

The data offset changes between reads, writes, and non-data commands. During writes, the value is CWL+2+slot#. During non-data commands, the value is 0. During reads, the value is calib_rd_data_offset_0/1/2 (found during DQSFOUND calibration) + slot#.

When using the MIG controller, the data offset values used during calibration and normal operation reads can be compared.The values should match for reads with even CWL, and be off by 1 for reads with odd CWL. This is because reads/writes are assigned to slot1 by the memory controller whereas slot0 is used for even CWL.

When using a PHY only design, the custom memory controller must send the data offset values to the PHY. The above calculations should be used based on the values found during DQSFOUND calibration, CWL, and Slot#. The MIG memory controller does not support non-zero AL values however, the PHY does. If the custom controller supports a non-zero AL, the write and read offsets need to additionally add the AL value. For example, mc_data_offset = calib_data_offset_0 + AL + Slot#.

As a general rule of thumb, the read data offset should be approximately CL + 4 or 5, which is the CL plus the round trip delay on the PCB.
AR# 47762
Date Created 05/08/2012
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Virtex-7 HT
IP
  • MIG 7 Series