AR# 47852 7 Series FPGAs GTP Transceivers - Known Issues and Answer Record List

This answer record lists the Known Issues and Answer Records associated with the 7 series FPGAs GTP transceivers.

Usage

(Xilinx Answer 44549) 7 Series FPGA GTX/GTH/GTP Transceivers - Reference clock phase noise masks
(Xilinx Answer 51017) 7 Series FPGA GTP Transceiver Power-Up/Power-Down
(Xilinx Answer 51448) 7 Series FPGA GTP Transceivers - RX Termination Use Modes
(Xilinx Answer 47975) 7 Series GTP Transceivers: BUFG/BUFH must be used between TX/RXOUTCLK and MMCM/PLL
(Xilinx Answer 43420) Xilinx Serial Transceivers - Can the LVDS standard be used for reference clocks?

Wizard

(Xilinx Answer 53396) 7 Series FPGAs Transceiver Wizard v2.4 - Known Issues and Release Notes
(Xilinx Answer 52263) 7 Series FPGAs Transceivers Wizard v2.3 - Known Issues and Release Notes
(Xilinx Answer 50827) 7 Series FPGAs Transceivers Wizard v2.2 - Known Issues and Release Notes
(Xilinx Answer 47477) 7 Series FPGAs Transceivers Wizard v2.1 - Known Issues and Release Notes
(Xilinx Answer 47492) 7 Series GTP Transceivers - Buffer bypass default attributes
(Xilinx Answer 46048) 7 Series FPGAs Transceivers Wizard - What silicon revisions are supported by different Wizard or ISE design tool versions?
(Xilinx Answer 50890) 7 Series FPGAs Transceivers Wizard Flow in Vivado Design Suite 2012.2/2012.3/2012.4

Implementation

(Xilinx Answer 47688) 7 Series FPGA GTP Transceiver - Implementation error in ISE 14.1/Vivado 2012.1 design tools when sharing reference clocks

Silicon Revision Specific

(Xilinx Answer 51369) Design Advisory for the Artix-7 FPGA GTP Transceiver - Attribute Updates, Issues, and Work-arounds for Initial/General Engineering Sample (ES) Silicon
(Xilinx Answer 53561) Design Advisory for Artix-7 FPGA GTP Transceivers: RX Reset Sequence Requirement for Production Silicon

Protocols

(Xilinx Answer 51402) 7 Series Integrated Block for PCI Express v1.6: Incorrect RX_CM_TRIM[4:0] setting for Artix-7 FPGAs

Answer Number	Answer Title	Version Found	Version Resolved
51017	Design Advisory for the Artix-7 GTP Transceiver Power-Up/Power-Down	N/A	N/A
51448	7 Series FPGA GTP Transceivers - RX Termination Use Modes	N/A	N/A
47975	7 Series GTP Transceivers - BUFG/BUFH must be used between TX/RXOUTCLK and MMCM/PLL	N/A	N/A
47492	7 Series GTH/GTP - BUFFER BYPASS Default Attribute	N/A	N/A
47688	7 Series FPGA GTP Transceiver - Implementation error in ISE 14.1/Vivado 2012.1 software when sharing reference clocks	N/A	N/A
51402	7 Series Integrated Block for PCI Express v1.6 - Incorrect RX_CM_TRIM setting for Artix-7 FPGAs	N/A	N/A
51369	Design Advisory for the Artix-7 FPGA GTP Transceiver - Attribute Updates, Issues, and Work-arounds for Initial/General Engineering Sample (ES) Silicon	N/A	N/A
53561	Design Advisory for Artix-7 FPGA GTP Transceivers: RX Reset Sequence Requirement for Production Silicon	N/A	N/A

AR# 47852
Date Created	05/11/2012
Last Updated	03/27/2013
Status	Active
Type	Known Issues
Devices	Artix-7
IP	7 Series FPGAs Transceivers Wizard

Feed Back

Description