The Zynq-7000 devices are documented in the Zynq data sheet, technical reference manual and other documents. Important design advisories and other considerations that transcend these documents are listed here. The source point for technical content begins in the Xilinx Zynq-7000 AP SoC Solution Center (Xilinx Answer 52512).
Design Advisories Alerted on February 18, 2013
(Xilinx Answer 47916) Answer Records related to errata items: Zynq-7000 AP SoC Devices - Silicon Revision Differences
(Xilinx Answer 53450) Design Advisory for Zynq-7000 AP SoC, USB - ULPI interface requires input hold time of 1 ns
(Xilinx Answer 54190) Design Advisory for Zynq-7000 AP SoC, APU - L2 cache Operation Requires Programming of the slcr.L2C_RAM Register
(Xilinx Answer 54195) Design Advisory for Zynq-7000 VCCPLL Sensitivity
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 52512 | Xilinx Zynq-7000 AP SoC Solution Center | N/A | N/A |
| 52010 | Zynq-7000 AP SoC - Documentation Summary | N/A | N/A |
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 47916 | Zynq-7000 AP SoC Devices - Silicon Revision Differences | N/A | N/A |
| 53450 | Design Advisory for Zynq-7000 AP SoC, USB - ULPI interface requires input hold time of 1 ns | N/A | N/A |
| 54190 | Design Advisory for Zynq-7000 AP SoC, APU - L2 cache Operation Requires Programming of the slcr.L2C_RAM Register | N/A | N/A |
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 47864 | Zynq-7000 AP SoC ZC702 Evaluation Kit - Known Issues and Release Notes Master Answer Record | N/A | N/A |