We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 47915

Design Advisory Master Answer Record for Zynq-7000 AP SoC Devices


The Zynq-7000 devices are documented in the Zynq data sheet, technical reference manual and other documents.

Important design advisories and other considerations that transcend these documents are listed here.

The source point for technical content begins in the Xilinx Zynq-7000 AP SoC Solution Center (Xilinx Answer 52512).


Design Advisory Alerted on August 8, 2016

(Xilinx Answer 66871)7 Series FPGA and Zynq-7000 AP SoC HR I/O Transition during power-on

Design Advisory Alerted on November 2, 2015

(Xilinx Answer 65688)Design Advisory for Zynq-7000 PS DDR: High temperature derating may be insufficient for LPDDR2 DRAM

Design Advisory Alerted on October 19, 2015

(Xilinx Answer 65145)Design Advisory for Zynq-7000 PS DDR- DDR3 CKE deassertion time is too short

Design Advisory Alerted on September 14, 2015

(Xilinx Answer 65240)Design Advisory for Zynq-7000 AP SoC: Power-On/-Off Sequence Requirements for PS eFUSE Integrity

Design Advisory Alerted on February 23, 2015

(Xilinx Answer 63149)Design Advisory for Zynq-7000 AP SoC: Secure Lockdown triggered by PS_POR_B reset sequence

Design Advisory Alerted on June 23, 2014

(Xilinx Answer 60848)Design Advisory for Zynq-7000 AP SoC: Static Memory Controller, Parallel (SRAM/NOR) Interface 64MB configuration issues


Design Advisory Alerted on June 2, 2014

(Xilinx Answer 60454)Design Advisory Zynq-7000 PS DDR Controller - DDR IO's are not properly configured in ISE/EDK and Vivado 2013.3 and earlier


Design Advisory Alerted on April 28, 2014

(Xilinx Answer 59999)Design Advisory for Zynq-7000 AP SoC, eMMC - JEDEC standard 4.41 requires input hold tie of 3 ns.

Design Advisories Alerted on December 9, 2013

(Xilinx Answer 57930)Design Advisory for Zynq-7000 SoC - Boundary Scan test fails when VMODE is set to 1.8V
(Xilinx Answer 58694)Design Advisory for Zynq-7000 SoC - Updated UG933 may require additional decoupling capacitors in some cases


Design Advisory Alerted on October 14, 2013

(Xilinx Answer 57744)Design Advisory for Zynq-7000 AP SoC - Zynq and QSPI reset requirements when using larger than 16MB flash


Design Advisory Alerted on September 16, 2013

(Xilinx Answer 57193)Design Advisory for the Artix-7, Kintex-7, Virtex-7, Zynq-7000 Packaging - The 7 Series Thermal Resistance Values (Theta-JA, Theta-JB, and Theta-JC) are being updated with more accurate values, many of which are substantially changed


Design Advisory Alerted on June 24, 2013

(Xilinx Answer 56195)Design Advisory for Zynq-7000 SoC - Why does a design that worked with ES silicon now fail to boot with production silicon?


Design Advisories Alerted on February 18, 2013

(Xilinx Answer 47916)Answer Records related to errata items: Zynq-7000 AP SoC Devices - Silicon Revision Differences
(Xilinx Answer 53450)Design Advisory for Zynq-7000 AP SoC, USB - ULPI interface requires input hold time of 1 ns
(Xilinx Answer 54190)Design Advisory for Zynq-7000 AP SoC, APU - L2 cache Operation Requires Programming of the slcr.L2C_RAM Register
(Xilinx Answer 54195)Design Advisory for Zynq-7000 VCCPLL Sensitivity


Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
52512 Xilinx Zynq-7000 AP SoC Solution Center N/A N/A

Child Answer Records

Associated Answer Records

AR# 47915
Date Created 05/15/2012
Last Updated 08/18/2016
Status Active
Type Design Advisory
  • Zynq-7000
  • EDK - 14.1
  • ISE Design Suite - 14.1
  • PlanAhead - 14.1
  • More
  • EDK - 14.4
  • EDK - 14.3
  • EDK - 14.2
  • PlanAhead - 14.2
  • PlanAhead - 14.3
  • Vivado Design Suite - 2015.2
  • Vivado Design Suite - 2015.1
  • Vivado Design Suite - 2014.4.1
  • Vivado Design Suite - 2014.4
  • Less