UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 47959

13.4 Timing Analysis Virtex-6 - Clock Arrival Times are Incorrect for Block Ram or FIFO Components

Description

When I analyze the timing paths to or from the Block Ram or FIFO, the clock arrival time for either the source or destination clock is incorrect and makes the requirement extra small. I should have a full cycle for these paths. When is this going to be fixed?

Solution

This issue is resolved in ISE Design Suite 14.1, but you must re-run implementation from NGDbuild.
AR# 47959
Date Created 05/17/2012
Last Updated 05/24/2012
Status Active
Type Known Issues
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6Q
  • Less
Tools
  • ISE Design Suite - 13.3
  • ISE Design Suite - 13.4