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AR# 4969

F1.5 Express/VHDL: multiple architectures for a single entity is not supported


Keywords: VHDL, Express, architecture, entity, configuration, synthesis

Urgency: Standard

General Description
FPGA Express does not support the use of a configuration statement within a
VHDL file to select between multiple architectures for a single entity. Only
one architecture may be linked to a particular entity declaration.


If multiple entities exist for a single architecture, Express will synthesize
the last one available, regardless of the configuration statement.
AR# 4969
Date 04/27/2007
Status Archive
Type General Article
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