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AR# 4972

FPGA Express - Inferred latches are using an LD_1 component instead of other primitives (LDCE, LDC)


Keywords: Foundation, FPGA, Express, Synopsys, latch, LD, LDC, LDCE, infer

Urgency: Standard

General Description:
FPGA Express always uses the LD_1 component when a latch is inferred in the HDL code. This may result in inefficient implementations if the latch includes a local reset or clock enable.


The only work-around is to instantiate the specific latch primitive desired. These components include LD, LDC, LDC_1, LDCE, and LDCE_1.

Consult the Xilinx Libraries Guide for a list of latch primitives for each family.
AR# 4972
Date Created 11/04/1998
Last Updated 08/11/2003
Status Archive
Type General Article