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AR# 50063 7 Series FPGA GTH Transceiver Initial ES Silicon - Link Margin Reduction

Description

In the 7 Series GTH transceiver Initial ES silicon, there can be up to 0.05 UI increase in TX output jitter and 0.05 UI decrease in RX input jitter tolerance for line rates up to 8.5 Gb/s when multiple GTH transceivers are used. Similarly, for line rates higher than 8.5 Gb/s, this can be up to 0.1 UI increase in TX output jitter and 0.1 UI decrease in RX input jitter tolerance when multiple channels are used.

Solution

Line-rates up to 8.5 Gb/s

If both ends of the link are 7 series FPGAs GTH transceivers, the link margin degradation could be up to 0.1 UI.

Line-rates above 8.5 Gb/s

If both ends of the link are 7 series FPGAs GTH transceivers, the link margin degradation could be up to 0.2 UI.

Supported Use Modes

For GTH transceiver line rates above 8.5 Gb/s and up to 10.3125 Gb/s, the maximum supported channel loss at Nyquist frequency is 25 dB when using the latest DFE attribute settings (PMA_RSV2, RX_BIAS_CFG, RXDFEXYDEN) in (Xilinx Answer 47128). Otherwise, the maximum supported channel loss is 20 dB.

For GTH transceiver line rates above 10.3125 Gb/s and up to 11.3 Gb/s, the maximum supported channel loss at Nyquist frequency is 20 dB.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47128 Design Advisory for the Virtex-7 FPGA GTH Transceiver - Attribute Updates, Issues, and Work-arounds for Initial Engineering Sample (ES) Silicon N/A N/A

Actions

AR# 50063
Date Created 05/24/2012
Last Updated 02/26/2013
Status Active
Type General Article
Devices
  • Virtex-7
  • Virtex-7 HT
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