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b. The 6 Ethernet PHY status LEDs are mounted to be visible through the metal bracket on the left edge of the KC705 when installed into a PCIe slot in a PC chassis. Cycle the KC705 board Power ON and OFF (using SW15), checking that all LEDs blink.
   
50079-25.jpg



c. If these LEDs above are not lit at power on, you might need to re-program the TI Power Controllers on your board. This can be done using the Texas Instruments Fusion Digital Power Manufacturing tool software package, the Texas Instruments USB Interface Adapter EVM, and the appropriate XML script.  
    For more details, see (Xilinx Answer 37561); open a Webcase with Xilinx Technical Support to receive the appropriate XML files (these are board specific).
    If you do not have a TI USB Interface Adapter EVM, you can follow the steps in (Xilinx Answer 54022) to order one at a significant discount.

d. If 12V Power LED (DS22) is not Green, then 12VDC is not being delivered to the KC705 power input connector. Follow these steps:

      
50079-4.jpg

3. Cable detection

    The KC705 uses a USB A-to-micro-B cable plugged into the KC705 Digilent USB-to-JTAG module, U58. A 2-mm JTAG header (J60) is also provided in parallel for access by Xilinx download cables such as Platform Cable USB II and Parallel Cable IV.

a. USB A-to-micro-B cable
     i.  Is the cable visible in Device Manager?  If the 3 items highlighted in the figure below are visible in Device Manager, this confirms that your USB cable is operational and has been correctly identified.

      

50079-16.jpg
    ii.  Are cable drivers loaded correctly?  Drivers for this cable should be included in the iMPACT installation.  However, if problems are experienced with USB A-to-micro-B cable connection, a Digilent plug-in can be downloaded from the link below.
         For installation, please follow the guidelines in the document provided in the downloaded files:
         http://digilentinc.com/Products/Detail.cfm?NavPath=2,66,768&Prod=DIGILENT-PLUGIN.
         This plug-in requires Adept systems 2.4 or later for Windows and Adept systems 2.3.9 or later for Linux. Adept software is available from Digilent:
         http://digilentinc.com/Products/Detail.cfm?NavPath=2,66,828&Prod=ADEPT2.
   iii.  Check system properties and environment variables. For information on environment variables, see (Xilinx Answer 11630).
    iv.  Is the USB port enabled?  You can reboot your system to re-initialize the USB buses.
     v.  Are Xilinx tools correctly installed?  (iMPACT or ChipScope Pro)  (For supported software version information, see the Kit Product Page: http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm)
          If an issue is suspected with tools installation, see Installation and Licensing Guide (make sure to use the most recent version of tools and associated documentation which supports the KC705).
    vi.  Is the Operating System (OS) being used Windows 7?  If so, please see (Xilinx Answer 41442) and (Xilinx Answer 44397).

b.  Platform Cable USB II
     i.  Is the cable visible in Device Manager?
   
54139-17.jpg
    ii.  Are the cable drivers loaded correctly?  Drivers for this cable should be included in the iMPACT installation.  However, if problems are experienced with the Platform Cable USB II connection, please follow the uninstall and reinstall instructions in (Xilinx Answer 44397).
   iii.  Check system properties and environment variables. For information on environment variables, see (Xilinx Answer 11630).
    iv.  Is the USB port enabled?  You can reboot your system to re-initialize the USB buses.  
      v. Are Xilinx tools correctly installed? (iMPACT or ChipScope Pro)  (For supported SW version information, see the Kit Product Page: http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm).
          If an issue is suspected with tools installation, see Installation and Licensing Guide (make sure to use the most recent version of tools and associated documentation which supports the KC705).
    vi.  Is the Operating System (OS) being used Windows 7?  If so, see (Xilinx Answer 41442) and (Xilinx Answer 44397).

c. Parallel Cable IV

    i.  Are the cable drivers loaded correctly?  For more information, see (Xilinx Answer 9984).
   ii.  If you receive the following message in iMPACT: "ERROR: Device Control LPT_WRITE_CMD_BUFFER Failed", see (Xilinx Answer 22293).
  iii.  Note: Parallel Cable IV speed cannot be modified in iMPACT 13.x and 12.x - see (Xilinx Answer 41808) for more details.
   iv.  If you cannot establish a connection with the Parallel Cable IV, see (Xilinx Answer 15742).

   If the above steps fail to enable you to connect, please open a Webcase to further debug the problem.
   In the Webcase notes, please include all debug steps taken to date.


4. JTAG Initialization

    The status of the board JTAG chain is checked using Xilinx Tools (iMPACT or ChipScope Pro). To check to see that the JTAG chain is initialized correctly, follow this JTAG Initialization Test Case:
  
    1. Remove any FMC cards from KC705.
    2. Set the mode switch SW13 for JTAG mode (101).
      

50079-26.jpg
    3. Power up KC705 on the bench (not in a PC chassis).
    4. Connect the Digilent USB A-to-micro B cable to the KC705 (through the Digilent onboard USB-to-JTAG configuration logic module - U59).
    5. Check that the Digilent device shows up in the Device Manager.
    6. Ensure Xilinx tools (ISE 13.4 or later - preferably the latest version of tools that support the KC705) are correctly installed.
    7. Launch iMPACT - is the cable identified correctly?
         a.  If not, see section 3. Cable detection above.
         b.  If yes, but iMPACT did not discover and display the JTAG chain, slow down the cable speed (Output > Cable Setup).
         c.  If yes, but iMPACT did not discover and display the JTAG chain and slowing the cable speed does not resolve the issue, see the following (assumes Digilent USB A-to-micro B cable is plugged into USB-to-JTAG configuration logic module U59):
    
50079-6.jpg

     If the above steps fail to enable you to initialize the JTAG chain, please disconnect the Digilent USB A-to-micro-B cable from the board and PC.  Connect the Platform Cable USB to header J4, and connect to your PC.
     Ensure Xilinx tools (preferably the latest version of tools that support the KC705) are correctly installed.  Launch iMPACT - is the cable identified correctly?   

     If the above steps fail to enable you to initialize the JTAG chain, please open a WebCase to further debug the problem.
     In the Webcase notes, please include all debug steps taken to date.

5. JTAG Configuration
  
    If JTAG chain initializes okay but JTAG configuration fails, check the following:
  
    a. Verify the mode switch settings for JTAG configuration mode:
         SW13-3   (M2)   1
         SW13-4   (M1)   0
         SW13-5   (M0)   1
    b.  In iMPACT, select a lower cable frequency (Output > Cable Setup) and re-attempt configuration
    c.  In iMPACT, run the Chain Integrity test by selecting Debug > Chain Integrity Test.  iMPACT will assist in the debugging of this scenario by providing insight into where the failing connection in the chain could be. 
    d.  Pulse the PROG push button on the KC705 (SW14).  Pulsing PROG will clear out any problems caused by power up ramp rate issues to the FPGA.
    e.  Read back the FPGA Status Register in iMPACT (Debug > Read Status Register).  The information extracted from the Status Register can help determine the stage of configuration and where a failure has occurred.  See (Xilinx Answer 24024) for more details.
    f.   Review (Xilinx Answer 34904) - Xilinx Configuration Solution Center.  The Configuration Solution Center is available to address all questions related to Configuration.

    If the above steps fail to enable JTAG configuration, please open a WebCase to further debug the problem.
    In the Webcase notes, please include all debug steps taken to date.
 

6. Master SPI configuration

The iMPACT tool can be used to indirectly program the Quad-SPI flash memory (U7) on the KC705. 
If you have loaded an ".mcs" file into the SPI flash on the KC705, and subsequent Master SPI configuration of the Kintex-7 device fails, the following points should be checked:

a.  If the ".mcs" file is correctly loaded, you will see the FPGA and the FLASH device in the JTAG chain, as shown here:

   

50079-17.jpg

     If you do not see the FLASH device attached to the xc7k325t as shown, see the iMPACT Help section of ISE Help.
b. Verify the mode switch settings for Master SPI configuration:
         S13-3     (M2)     0
         S13-4     (M1)     0
         S13-5     (M0)     1
c. In iMPACT, select a lower cable frequency and re-attempt configuration.
d. Pulse the PROG push button on the KC705 (SW14), to attempt to reload the FPGA with the configuration image.
e.  Review (Xilinx Answer 34904) - Xilinx Configuration Solution Center.  The Configuration Solution Center is available to address all questions related to Configuration.

    NOTE: KC705 Rev C has an N25Q256 SPI device on board, whereas KC705 Rev 1.0 has an N25Q128 SPI device on board.

    If the above steps fail to enable SPI configuration, please open a WebCase to further debug the problem.
    In the WebCase notes, please include all debug steps taken to date.

7. Master BPI configuration

The iMPACT software tool can be used to indirectly program the BPI flash memory (U58) on the KC705. 

a.  To confirm the BPI interface on the board is working using a known working example design, download and run the KC705 Restoring Flash Contents Design Files, whichever version is appropriate for your silicon and software version.  
     It is recommended to always use the latest version of software which supports the KC705, and the associated version of the KC705 Restoring Flash Contents Design Files.
     Follow the associated PDF.  All are available from the KC705 Example Designs page.

50079-27.jpg
     To identify the silicon version of your kit (C or CES), see (Xilinx Answer 37579).
b.  Read the KC705 Restoring Flash Contents design document:: KC705 Restoring Flash Contents PDF: xtp131pdf; KC705 Restoring Flash Contents Vivado PDF: xtp198.pdf and follow the instructions therein.

    If U58 (BPI Flash) on the KC705 contains an image (the as-shipped BIST image or a user-programmed image) and the Kintex-7 FPGA does not configure as expected from the BPI flash, then the following points should be checked:

c. If the ".mcs" file is correctly loaded, you will see the FPGA and the FLASH device in the JTAG chain, as shown here:

   

50079-17.jpg
     If you do not see the FLASH device attached to the xc7k325t, as shown, see the iMPACT Help section of ISE Help.
d. Verify the mode switch settings for Master BPI configuration:
          S13-3 (M2) 0
          S13-4 (M1) 1
          S13-5 (M0) 0
e.  In iMPACT, select a lower cable frequency and re-attempt configuration.
f.  Pulse the PROG push button on the KC705 (SW14), to attempt to reload the FPGA with the configuration image.
g.   Review (Xilinx Answer 34904) - Xilinx Configuration Solution Center.  The Configuration Solution Center is available to address all questions related to Configuration.

     If the above steps fail to enable BPI configuration, please open a WebCase to further debug the problem.
     In the WebCase notes, please include all debug steps taken to date.

8. XADC

a.  Verify XADC jumper settings - see Section 1. Switch / Jumper Settings, part e, above.
b.  Ensure Xilinx tools (latest version which supports KC705) are correctly installed on your machine.
c.  To test the XADC interface on the KC705, use a known working reference design. If you have access to the AMS101 Evaluation Card (shown below) with the KC705, download and run the Kintex-7 FPGA KC705 Evaluation Kit AMS Targeted Reference Design (latest version) to check the XADC functionality. 
    

50079-23.jpg
     Please ensure you have the correct version of Vivado Design Suite installed to run this TRD. It is recommended to always use the latest version of software, TRD, and associated documentation (7 Series FPGA AMS Targeted Reference Design User Guide).
     You can download this Targeted Reference Design, as well as the AMS Evaluator Installer and Documentation for this TRD, from the KC705 Documentation page.
d.  Details on XADC operation can be found in UG480 and UG772.  Be sure to use the most recent version of the document).
     
     If the above steps fail to resolve the XADC issue, please open a WebCase to further debug the problem.   
     In the WebCase notes, please include all debug steps taken to date.

9. PCIe

     If the KC705 configures correctly, however the PCIe interface does not operate as expected, check the following:

a. Do NOT plug a PC ATX power supply 6-pin connector into J49 on the KC705 board.  The ATX 6-pin connector has a different pinout than J49.  Connecting an ATX 6-pin connector into J49 will damage the KC705 board and void the board warranty.
    To install and power the board correctly, follow the instructions given in UG810 KC705 Evaluation Board User Guide - Appendix D - Board Setup.
b. If you are using a Z77 (Ivy Bridge) platform, and are attempting to run the KC705 Targeted Reference Design, please see (Xilinx Answer 52657) - Kintex-7 FPGA KC705 Evaluation Kit - Targeted Reference Design - PCIe does not link up on Z77 (Ivy Bridge) platform.
c. Check J32, lane width, is set correctly for your application.
d.  See (Xilinx Answer 44353) - 7 Series Integrated Block for PCI Express - How to Target the Kintex-7 Integrated Block Wrapper to the KC705 Boards.
e.  See (Xilinx Answer 40469) - 7 Series Integrated Block for PCI Express - Release Notes and Known Issues for All Versions affecting PCIe and 7 series, including Kintex-7.
f.   Download and run the KC705 PCIe Example Design, whichever version is appropriate for your silicon and software version.  It is recommended to always use the latest version of software which supports the KC705, and associated version of the KC705 PCIe Example Design.
     Follow the associated PDF.  All are available from the KC705 Example Designs page.

  

50079-8.jpg
     To identify the silicon version of your kit (C or CES), see (Xilinx Answer 37579).
g.  Read the KC705 PCIe Example Design document: KC705 PCIe PDF: xtp106.pdf; KC705 PCIe Vivado PDF: xtp197.pdf and follow the instructions therein.
h.  Review (Xilinx Answer 34536) - Xilinx Solution Center for PCI Express.  The Solution Center for PCI Express is available to address all questions related to the Xilinx solutions for PCI Express.

      If the above steps fail to resolve the PCIe issue, please open a WebCase to further debug the problem.
      In the WebCase notes, please include all debug steps taken to date.


10. IBERT

      NOTE: Running IBERT requires the installation of ChipScope Pro.  A device-locked license for this software is provided with the Kintex-7 FPGA KC705 Evaluation Kit.
      If the KC705 configures correctly, however IBERT does not operate as expected, check the following:

a.   If using MGT loopback, ensure you have the correct equipment, including SMA cables, SMA Quick connects and Connect Optical Loopback Adapter:

50079-21.jpg
50079-20.jpg
50079-22.jpg 

      More information can be found in the KC705 GTX IBERT PDF or KC705 GTX IBERT VIVADO PDF, from the KC705 Example Designs page.
b.   Download and run the KC705 GTX IBERT Example Design, whichever version is appropriate for your silicon and software version.  It is recommended to always use the latest version of software which supports the KC705, and associated version of the KC705 GTX IBERT Example Design.
      Follow the associated PDF.  All are available from the KC705 Example Designs page.
   

50079-9.jpg
      To identify the silicon version of your kit (C or CES), see (Xilinx Answer 37579).
c.   Read the KC705 GTX IBERT Example Design document: KC705 GTX IBERT PDF: xtp103.pdf; KC705 GTX IBERT Vivado PDF: xtp200.pdf and follow the instructions therein.
d.   IBERT Design Assistant: (Xilinx Answer 45562).
e.   Review (Xilinx Answer 45201) - Xilinx ChipScope Solution Center - IBERT Design Assistant.  The ChipScope Solution Center is available to address all questions related to ChipScope.

      If the above steps fail to resolve the IBERT issue, please open a WebCase to further debug the problem.
      In the WebCase notes, please include all debug steps taken to date.



11. Multiboot


      If KC705 initial configuration was successful, however Multiboot is not working as expected, check the following:

a.  Verify steps taken to program KC705 with Multiboot bitstream in iMPACT (if using a custom bitstream); please refer to UG470.
b.  Download and run the KC705 Multiboot Example Design, whichever version is appropriate for your silicon and software version.  It is recommended to always use the latest version of software which supports the KC705, and associated version of the KC705 Multiboot Example Design.
     Follow the associated PDF.  All are available from the KC705 Example Designs page.
 
50079-10.jpg
     To identify the silicon version of your kit (C or CES), see (Xilinx Answer 37579).
c.  Read the KC705 Multiboot Example Design document: KC705 Multiboot PDF: xtp104.pdf; KC705 Multiboot Vivado PDF: xtp201.pdf

     If the above steps fails to resolve the Multiboot issue, please open a WebCase to further debug the problem.
     In the WebCase notes, please include all debug steps taken to date.


12. DDR3

      If a problem is suspected with DDR3 / MIG, check the following:

a.  Ensure DDR3 DIMM module is inserted correctly.
b.  Download and run the KC705 MIG Example Design, whichever version is appropriate for your silicon and software version.  It is recommended to always use the latest version of software which supports the KC705, and associated version of the KC705 MIG Example Design.
     Follow the associated PDF.  All are available from the KC705 Example Designs page.
  
50079-11.jpg
     To identify the silicon version of your kit (C or CES), see (Xilinx Answer 37579).
c.  Read the KC705 MIG Example Design document: KC705 MIG PDF: xtp105.pdf; KC705 MIG Vivado PDF: xtp196.pdf
d.  Review (Xilinx Answer 34243) - Xilinx MIG Solution Center.  The Memory Interface Generator (MIG) Solution Center is available to address all questions related to MIG.

     If the above steps fail to resolve the DDR3 issue, please open a WebCase to further debug the problem.
     In the WebCase notes, please include all debug steps taken to date.



13. Interface Tests

      (Xilinx Answer 54279) - Kintex-7 FPGA KC705 Evaluation Kit - Interface Test Designs can be run to ensure that the interfaces on the KC705 are working correctly.  This Answer Record forms part of (Xilinx Answer 43748) - Xilinx Boards and Kits Debug Assistant.
      If the above tests fail to resolve the issue, please open a WebCase to further debug the problem.
      In the WebCase notes, please include all debug steps taken to date.



14. Known Issues for KC705
     
      All Known Issues for the Kintex-7 FPGA KC705 Evaluation Kit are listed in (Xilinx Answer 45934) - Kintex-7 FPGA KC705 Evaluation Kit - Known Issues and Release Notes Master Answer Record.
      If the issue you are faced with is not listed in the Known Issues and Release Notes Master Answer Record, and the steps above fail to resolve the issue, please open a WebCase to further debug the problem.
      In the WebCase notes, please include all debug steps taken to date.