UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 50092

14.1 EDK - Clock Generator 4.03a produces invalid HDL

Description

The following error occurs when clock_generator is configured as CLKOUT5_BUF = TRUE.
ERROR:HDLCompiler:69 - "/proj/xhd_edk_tools/users/jaipalr/EDK/reg/hdl_error/2/hdl/elaborate/clock_generator_0_v4_03_a/hdl/vhdl/clock_generator.vhd" Line 676: <sig_mmcm0_false> is not declared.
ERROR:HDLCompiler:854 - "/proj/xhd_edk_tools/users/jaipalr/EDK/reg/hdl_error/2/hdl/elaborate/clock_generator_0_v4_03_a/hdl/vhdl/clock_generator.vhd" Line 61: Unit <structure> ignored due to previous errors.
ERROR:EDK:546 - Aborting XST flow execution!
INFO:EDK:2246 - Refer to
/proj/xhd_edk_tools/users/jaipalr/EDK/reg/hdl_error/2/synthesis/system_clock_
generator_0_wrapper_xst.srp for details
Running NGCBUILD ...
INFO:EDK:3509 - NCF files should not be modified as they will be regenerated.
If any constraint needs to be overridden, this should be done by modifying
the data/system.ucf file.
Rebuilding cache ...
ERROR:EDK:440 - platgen failed with errors!
make: *** [implementation/system_proc_sys_reset_0_wrapper.ngc] Error 2
Done!

Solution

This is a known issue with the Clock Generator IP and is to be fixed in version 14.2 of the tools.

As a work-around, you can revert to 13.4, or bring an older version of the Clock Generator core into your design.

AR# 50092
Date Created 11/13/2012
Last Updated 11/13/2012
Status Active
Type General Article
Tools
  • EDK - 13
  • EDK - 14
IP
  • Clock Generator