Vivado Synthesis, when synthesizing an RTL design containing a unimacro module, will generate a netlist with the same name as the actual unimacro module present in the RTL design. As a result, post synthesis simulations (when run with -L unimacro switch) will fail as it will end up using the unimacro module present in the actual unimacro library. There are couple of work-arounds available for this problem:
- -L unimacro switch should not be passed when running a post synthesis simulation containing an instantiated unimacro module.
- Modify the instantiated unimacro module name to make it unique by editing the post synthesis netlist generated from the Vivado synthesis tool.
This issue will not be fixed in Vivado Synthesis. The plan is to withdraw Vivado Synthesis support for unimacro.