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AR# 50147 7 Series FPGA GTH Transceivers Resistor Calibration

Description

This answer record covers the GTH resistor calibration and the necessary workaround for the 7 series FPGA GTH transceivers.

Solution

Update: There is no issue with the GTH resistor calibration circuitry based on further investigation and analysis. The following workaround is not required and should be removed. This answer record will be obsoleted in the future. The GTH resistor calibration circuitry on the Initial ES silicon devices may not calibrate to the expected value. The following workaround must be followed to enable correct GTH RX and TX termination.
  1. Read the RCAL value on Channel DRP address (x105 [12:8]) (One RCAL per column) (there is no attribute equivalent for this).
  2. Change the BGRCALOVRDENB port to 1'b0.
  3. Change the BGRCALOVRD port to 5d18.
  4. Follow the steps below:

i. Write 3'd7 on Channel DRP address x06A[15:13] (attribute name is TERM_CAL_OVRD[2:0])
ii. Use the RCAL value obtained in Step 1to get the correct override value based on the look-up table below.
iii. Override the RCAL value at Channel DRP address x069[14:0] (attribute name is TERM_RCAL_CFG[14:0]) with the value above in (ii).


RCAL code from Step 1, x105[12:8]Override value
Decimalbinaryx069 [14:0] [TERM_RCAL_CFG] value
05b0000015h4A52
15b0000115h4631
25b0001015h4210
35b0001115h3DEF
45b0010015h39CE
55b0010115h35AD
65b0011015h318C
75b0011115h2D6B
85b0100015h294A
95b0100115h2529
105b0101015h2108
115b0101115h1CE7
125b0110015h18C6
135b0110115h14A5
145b0111015h1084
155b0111115h0C63
165b1000015h0842
175b1000115h0421
185b1001015h0000
195b1001115h7FFF
205b1010015h7BDE
215b1010115h77BD
225b1011015h739C
235b1011115h6F7B
245b1100015h6B5A
255b1100115h6739
265b1101015h6318
275b1101115h5EF7
285b1110015h5AD6
295b1110115h56B5
305b1111015h5294
315b1111115h4E73

Actions

AR# 50147
Date Created 05/24/2012
Last Updated 07/27/2012
Status Active
Type
Devices
  • Virtex-7
  • Virtex-7 HT
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