There is a handshake between the PCIe core of the Tandem design and the rest of the design. The PCIe IP core provides a signal called "user_app_rdy" which indicates when the second stage has completed loading. There is a delay between when the second stage is alive and user_app_rdy asserts. This delay has not been characterized yet. How this works is -
(1) 2nd stage comes alive after Startup and logic generates a predetermined alternating pattern
(2) Logic in 1st stage looks for this pattern and begins a countdown when detected
(3) When counter finishes, 1st stage asserts a signal user_app_rdy (may be used as a 2nd stage "Done")
The signals used are -
User_clock_out - output from PCIe core to other logic
User_app_rdy - output from PCIe core to other logic, enabled when PCIE core detects pattern from other logic
INIT_PATTERN_BUS - bus from other logic into PCIe core to show that second stage logic is "alive"