We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 50163

Tandem Configuration - What signals are added to my design by using the Tandem solution?


If I use the Tandem PROM/PCIe solution for fast configuration over PCIe are there any signals added to my design?


The core and example design contain ports (signals) specific to Tandem Configuration. These signals provide handshaking between the first stage (the core) and the second stage (user logic). These signals can coordinate events in the user application. Following is some additional information about these signals:

  • user_clk is simply the main internal clock for the PCIe IP core. Use this clock to synchronize any user logic that communicates directly with the core.
  • user_reset can likewise be used to reset any logic that communicates with the core when the core itself is reset.
  • user_app_rdy is related to user_reset. user_reset is issued first, and user_app_rdy asserts 2 to 12 clock cycles after user_reset deasserts. The delay ensures that user_app_rdy is not asserted in the middle of a PCIe transaction.

In addition to these interface signals, the PCIe IP module interface replicates the ports for the ICAP (Tandem PCIe only) and STARTUP blocks, as these blocks are instantiated within the IP core. Look for the icap_* and startup_* ports to connect any user application to these blocks. The only requirement is that the user application must not access these ports until user_app_rdy has been asserted, meaning the design is fully operational.

AR# 50163
Date Created 05/25/2012
Last Updated 06/17/2013
Status Active
Type General Article
  • Vivado Design Suite - 2013.2
  • 7 Series Integrated Block for PCI Express (PCIe)
  • Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)