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AR# 50188

Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 (ISE 14.1 / Vivado 2012.1) - The Core fails to come out of the Disabled State

Description

Version Found: v1.1
Version Resolved and other Known Issues: See (Xilinx Answer 47441)

When the core is directed by a higher layer to go into the Disabled state, the core never comes out of this state. The main purpose of the Disabled state is to allow a configured link to be disabled until directed, or Electrical Idle is exited (for instance, due to a hot removal and inserter) after entering Disabled state (Ref: PCI Express Base Specification Rev 3.0).

Solution

This is a known issue to be fixed in a future revision of the core.

NOTE: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
05/31/2012 - Initial release

AR# 50188
Date Created 06/06/2012
Last Updated 08/26/2013
Status Active
Type Known Issues
Tools
  • Vivado Design Suite - 2012.1
  • ISE Design Suite - 14.1
IP
  • Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)