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AR# 50189

Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 (ISE 14.1 / Vivado 2012.1) - Default value for TX Preset Settings not used


Version Found: v1.1
Version Resolved and other Known Issues: See (Xilinx Answer 47441)

In the current core version, the default TX Preset Settings values are not used. The values need to be set manually. To disable Manual Equalization Control by default, set pipe_rxeq_user_en to 8'h00 in the pcie_3_0_7vx.v file.


This is a known issue to be fixed in a future revision of the core.

Note: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
05/31/2012 - Initial release

AR# 50189
Date Created 06/06/2012
Last Updated 08/27/2013
Status Active
Type General Article
  • Vivado Design Suite - 2012.1
  • ISE Design Suite - 14.1
  • Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)